The present invention relates to an improved apparatus and method for extending data retention time of a semiconductor storage circuit comprising a DRAM (dynamic random access memory).
Recently more and more information equipment have been developed as portable equipment driven by an internal battery. In such portable equipment, it is desired to further decrease power consumption of a semiconductor storage circuit, that is, one of the internal elements of the portable equipment, so as to extend the time for driving the internal elements by the internal battery.
A DRAM included in the semiconductor storage circuit requires a periodic refresh operation for recovering the original state of stored charge even when the DRAM is not operated, i.e., it is in the standby state, because a stored data, i.e., the stored charge, leaks owing to its structural characteristic. When the interval of the refresh operation can be set longer, the amount of a current consumed in the standby state can be decreased and the lifetime of the internal battery of the portable equipment can be elongated.
Now, the configuration of the main part of a DRAM and the leakage path of the stored charge therein will be described.
FIG. 25 shows the main part configuration of a DRAM. In FIG. 25, a reference character "a" denotes a memory cell and a reference character "b" denotes a memory cell array including a large number of memory cells (a). Each memory cell (a) includes a memory cell transistor (c) and a memory cell capacitor (d). The memory cell transistor (c) is connected to a word driver circuit (e) through a word line WL at its gate electrode G and is also connected to a sense amplifier (f) through a bit line BL at its first electrode (q). A second electrode (t) of the memory cell transistor (c) is connected to one electrode of the memory cell capacitor (d), thereby forming a charge storage node (j). The charge storage node (j) stores charge of a predetermined potential VSN as a data. For example, when a data is at a high level, the charge storage node (j) is charged to a voltage VSN equal to a voltage Vcc (wherein the voltage Vcc is a supply voltage of, for example, 3.6 V), and when a data is at a low level, the node is charged to a voltage VSN of 0 V. The other electrode of the memory cell capacitor (d) is connected to a cell plate node (g), to which a predetermined cell plate node potential Vcp (for example, of 1.8 V) is applied by a memory cell plate potential generating circuit (h). A substrate node (i) of the memory cell transistor (c) is supplied with a predetermined substrate node potential VBB (for example, of -1.5 V).
FIG. 27 shows the charge leakage path from the memory cell transistor (c). The memory cell transistor (c) shown in this figure is formed as an N-channel MOS transistor. As is shown in FIG. 27, the charge storage node (j) is connected to the substrate node (i) via a PN junction (k) formed between a P-type substrate and an N-type diffused layer of the memory cell transistor (c). Therefore, when the charge storage node (j) stores a high data (VSN=3.6 V), the stored charge leaks via the PN junction (k) to the P-type substrate and flows to the substrate node (i) (VBB=-1.5 V). Additionally, in the case where the memory cell transistor (c) is in an off state, when the potential of the first electrode (q) is lower than that of the second electrode (t), the first electrode (q) works as a source and the second electrode (t) works as a drain, thereby forming a charge leakage path Lp1 from the second electrode (t) to the first electrode (q). When the potential of the second electrode (t) is lower, the second electrode (t) works as a source and the first electrode (q) works as a drain, thereby forming a charge leakage path Lp2 from the first electrode (q) to the second electrode (t). Therefore, when the charge storage node (j) stores a high data (VSN=3.6 V), the stored charge leaks from the second electrode (t) through the leakage path Lp1 to the first electrode (q). When the charge storage node (j) stores a low data (VSN=0 V), the charge of the first electrode (q) flows through the leakage path Lp2 to the second electrode (t). Accordingly, when, for example, a high data is stored as is shown in FIG. 26, after refreshing a predetermined one of the memory cells, it is necessary to perform the next refresh operation of that memory cell before the potential VSN of the charge storage node (j) of that memory cell decreases to a limit potential Vlim ("H") for reading a high data. When the decreasing rate of the potential VSN of the charge storage node is smaller (namely, when the charge leakage amount from the charge storage node (j) is smaller), the refresh interval can be set longer and the amount of a current consumed in the standby state can be decreased.
The charge leakage amount from the charge storage node (j) varies in the respective memory cells. Therefore, the refresh interval is generally set sufficiently long for a memory cell having the largest leakage amount.
As a countermeasure, it is possible to replace a defective memory cell having a large leakage amount with a good memory cell having a small leakage amount in the memory cell array (b). However, when a DRAM has a large capacity, the number of defective memory cells therein is increased. Therefore, the replacement of all the defective memory cells with redundant memory cells cannot be a practical countermeasure in view of the increase of a redundant area.
In the conventional technique disclosed in, for example, Japanese Laid-Open Patent Publications Nos. 4-179164 and 5-291534, the potential of the charge storage node (j) is recovered to its original value priorly to the operation of the DRAM even when the potential is varied owing to the charge leakage via the PN junction. This technique is based on passive concept that the charge leakage is to be tolerated. In contrast, for example, Japanese Laid-Open Patent Publication No. 6-111567 (Conventional Example 1) discloses an active technique to limit the leakage amount, in which a potential difference between the both ends of the PN junction is suppressed, thereby suppressing the leakage current flowing through the PN junction. This publication describes a method to suppress the potential difference at the PN junction as follows: The potential of the cell plate node (g) is lowered, thereby decreasing the potential of the charge storage node (j) due to capacity coupling of the memory cell capacitor (d). Thus, a potential difference between the charge storage node (j) and the substrate node (i) (that is, the potential difference at the PN junction) is minimized.
Furthermore, "A 34ns 256 Mb DRAM with Boosted Sense-Ground Scheme" (1994, IEEE International Solid-State Circuits Conference/SESSION 8/DRAMS AND NON-VOLATILE MEMORIES/PAPER TA8.2) (Conventional Example 2) discloses a technique to suppress a leakage current (off current) flowing between the drain and the source of the memory cell transistor (c) in an off state. In this technique, at the standby time when the potential of the word line is "0", the potential of the bit line BL is set to be slightly higher than "0". Since the potential of the bit line BL is thus set at the standby time, a potential difference Vgs between the gate and the source of the memory cell transistor (c) (Vgs=a gate potential Vg-a source potential Vs) becomes a negative potential when the first electrode (q) (which is connected to the bit line BL) of the memory cell transistor (c) works as a source. This enhances the off state of the memory cell transistor (c), thereby effectively decreasing the amount of the off current flowing from the charge storage node (j) through the memory cell transistor (c) to the bit line BL.
However, when both the leakage current through the PN junction and the off current through the memory cell transistor (c) are to be actively decreased, a combination of Conventional Examples 1 and 2 leads to the following problem:
In Conventional Example 1, when the charge storage node (j) stores a low data (VSN=0 V), the potential of the node (j) is decreased to be negative in accordance with the potential decrease of the cell plate node (g) at the standby time. At this point, since the second electrode (t) (which is connected to the charge storage node (j)) of the memory cell transistor (c) works as a source and the gate-source voltage Vgs becomes positive, the memory cell transistor (c) is turned on. As a result, a current flows from the bit line BL through the memory cell transistor (c) to the charge storage node (j), thereby increasing the potential of the charge storage node (j). Thus, the low data is destroyed. Such a problem does not occur when the charge storage node (j) stores a high data. When the data is at a high level, the first electrode (q) (which is connected to the bit line BL) of the memory cell transistor (c) works as a source, and hence, the configuration of Conventional Example 2 exhibits its effect. As a result, the off state of the memory cell transistor (c) is enhanced, thereby suppressing the off current flowing from the charge storage node (j) through the memory cell transistor (c) to the bit line BL. Thus, the high data stored in the charge storage node (j) can be successfully retained.
In addition, the technique of Conventional Example 2 can be more effective than the technique of Conventional Example 1 in some cases. When a transistor having an SOI (silicon on insulator) structure is adopted as a memory cell transistor as is shown in FIG. 16, an insulator is disposed between a P-type substrate and two electrodes. Therefore, no PN junction exists in such a case, and hence, there is no need to pay attention to a leakage current through the PN junction. Furthermore, when a memory cell transistor is refined, voltage resistance of a gate oxide film is decreased, and hence it is necessary to set low a voltage to be applied thereto. This results in the decrease of a threshold voltage of the memory cell transistor, and an off current flowing through the memory cell transistor can be estimated to be large. In such a case, it is important to suppress the off current flowing through the memory cell transistor by means of the technique of Conventional Example 2, but there can be a case where Conventional Example 2 cannot be applied for the following reason: When the respective memory cells (a) are intensively refreshed during the standby time, there exists a halt period when no refresh operation is conducted. In the halt period, the bit line BL is generally precharged to a supply voltage or an intermediate potential (a potential of 1/2 of the supply voltage). In this case, it is impossible to adopt the technique of Conventional Example 2, in which the potential of the bit line is set to be slightly higher than 0 with the potential of the word line being 0. In this case, when the charge storage node (j) stores a low data, the second electrode (t) (which is connected to the charge storage node (j)) of the memory cell transistor (c) works as a source, and hence, the memory cell transistor (c) is turned on. As a result, a current flows from the bit line BL through the memory cell transistor (c) to the charge storage node (j), which can disadvantageously destroy the low data.
A DRAM includes memory cells storing low data as well as those storing high data. Therefore, it is impossible to suppress the leakage current through the PN junction or the off current through the memory cell transistor by these conventional technique without destroying the data.
The present invention was devised to overcome the aforementioned problems, and its object is to suppress a leakage current through a PN junction or an off current through a memory cell transistor without destroying a low or high data stored in each charge storage node, so as to extend the data retention time. Thus, a refresh interval can be set longer and current consumption of an internal battery of portable equipment can be decreased.